1. Technical Field of the Invention
The present invention discloses concatenated BCH codes for a forward error correction coder and decoder (CODEC) for use in digital communication systems.
2. Background of the Invention
Long-distance digital communication systems, such as optical submarine cable systems, are responsible for the transmission of significant amounts of data. This data is transmitted across great distances, often from continent to continent. During transmission, data can become corrupted from noise within transmission channels, faults in transmission or receiving devices, or data errors from reading to and writing from an elastic store. Therefore, forward error correction (FEC) is employed to minimize the error probability of the data being transmitted.
Claude Shannon first suggested a maximum possible channel throughput which developed into a theorem of error correction describing the addition of redundant data to payload data for the correction of errors from channel noise or interference during transmission. Such forward error correction increases the reliability of transmitted data by encoding a block of payload data with redundant data bits through an algorithm generated at the transmitter, which allows a decoder to determine if an error has occurred at the receiver. The decoder employs the code generated by the encoder to identify what information, if any, has been corrupted by noise or interference during transmission, and the decoder can correct these errors.
Two common methods of FEC coding are block coding and convolutional coding; the present invention employs the former, where a codeword (n) is the block of symbols that carries the information symbols (k) and the redundant symbols (r). Each symbol is comprised of data words of m bits. In block coding, where n−k=r, redundancy symbols (r) are added to information symbols (k), originating from the encoder at the transmitter, and the redundancy symbols are utilized by the decoder at the receiver to correct transmission errors. Generally, errors in long-distance data transmission are uniformly random. Such errors can be remedied by interleaving bits for transmission; therefore, errors are scattered across transmission frames so that de-interleaving the data shows random, individualized errors which are easy to detect and correct.
While increasing the number of bits in a symbol may increase the ability for FEC to correct errors, it also increases circuit size and the amount of power required. Therefore, more efficient FEC can be accomplished by concatenated codes, which combine two or more FEC codes, physically layered as an inner and an outer code, such that the inner code comprises an encoder or decoder and the outer code comprises an encoder or decoder.
The present invention is comprised of a serial concatenation of binary Bose-Ray-Chaudhuri-Hocquenghem (BCH) codes. BCH codes are cyclic, error-correcting, digital codes of varying length which are able to correct errors. BCH codes typically employ a polynomial over a finite field, and a BCH codeword consists of a polynomial that is a multiple of the generator polynomial, which specifies a maximum length Linear Feedback Shift Register (LFSR). At the transmitter, the outer code encodes the data, followed by the inner code. Such concatenated codes are desirable as they are effective against both random and burst errors: first, the inner code decodes the data at the receiver; then the outer code decodes the same data. Employing such iterative decoding allows the outer code to correct any remaining errors not corrected by the inner code. The redundancy required for such error correction is attained by the addition of extra bits, or redundancy bits, to blocks of information, and transmitting the combined bits at a higher data rate.
Unlike some prior art, the present invention does not intend to match the RS(255,239) code standardized by ITU-T G.975.1, and requires less overhead. In addition, unlike some prior art, the present invention does not necessarily reserve any number of redundancy bits for predetermined tasks, but allows the redundancy bits to be unrestricted and available for use as needed. The present invention specifically employs BCH codes, differing from some prior art which may also employ Reed-Solomon, Reed-Muller, Cyclic Redundancy Check, Hamming, Viterbi Golay, Turbo, Fire Turbo, or other error correction codes. The present invention also relies upon the specific BCH(3896, 3824) and BCH(2040, 1952) codes.